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[Other resource] flowadd

Description: verilog编写的32位浮点加法器-32-bit Floating Point Addition Written in Verilog
Platform: | Size: 1442 | Author: 张桓铭 | Hits:

[VHDL-FPGA-Verilog] flowadd

Description: verilog编写的32位浮点加法器-32-bit Floating Point Addition Written in Verilog
Platform: | Size: 1024 | Author: 张桓铭 | Hits:

[MPI] floatmul

Description: 采用VERILOG 语言进行设计 实现32位浮点数乘法运算 结果已经验证过 放心使用-Verilog design language used to achieve 32-bit floating-point multiplication results have been verified ease of use
Platform: | Size: 1024 | Author: NOVEI | Hits:

[VHDL-FPGA-Verilog] flowadd

Description: 两个浮点数相加的加法器，使用verilog编写-Addition of two floating-point adder, the use of Verilog to prepare
Platform: | Size: 1024 | Author: 蔡大 | Hits:

[Embeded-SCM Develop] floating_point_verilog

Description: verilog写的浮点运算加法，希望对大家有用处-verilog to write floating point addition, we want to be useful
Platform: | Size: 1024 | Author: dupengcheng | Hits:

[VHDL-FPGA-Verilog] floating_point_addition_subtraction

Description: Simple floating point addition unit written in Verilog
Platform: | Size: 3072 | Author: binh | Hits:

[VHDL-FPGA-Verilog] Floating-Point-Adder

Description: 浮点数加法器IP核的vhd设计。浮点数加法运算是运输中使用最高的运算，结合vhdl和EPGA可编程技术，完成具有5线级流水线结构、符合IEEE 754浮点标准、可参数化为单、双精度的浮点数加法器。-Floating point adder design IP core vhd. Floating-point addition operation is used in most transport operations, combined with vhdl and EPGA programmable technology, complete with 5 line-stage pipeline structure to meet IEEE 754 floating point standards, parameters into a single, double precision floating point adder.
Platform: | Size: 154624 | Author: 凌音 | Hits:

[VHDL-FPGA-Verilog] canbus

Description: CAN总线的FPGA实现，用Verilog编写，代码完整，而且有很完善的测试代码，用ISE直接打开，学习FPGA进阶的好项目-CAN Bus FPGA, written with Verilog, code integrity, but also very good test code, using ISE directly open, a good project to learn advanced FPGA
Platform: | Size: 863232 | Author: 张小琛 | Hits:

[VHDL-FPGA-Verilog] Float_add

Description: 该源码利用Verilog HDL语言成功实现了浮点数的加法运算，包括全部工程以及Verilog 源码，经验证，该程序成功实现了浮点数的加法。-The use of Verilog HDL source language of the successful implementation of floating-point addition operation, including all engineering and Verilog source code, proven, successful implementation of the program the floating point adder.
Platform: | Size: 12144640 | Author: zhu yue | Hits:

[VHDL-FPGA-Verilog] Verilog_add_div_multi_exp

Description: 使用verilog写的32位浮点数加法模块、浮点数乘法模块、浮点数除法模块、浮点数指数模块。指数模块是综合前面三个例化成泰勒级数求指数，迭代次数（可设置）决定了精度。-Use verilog write 32-bit floating-point addition module, floating-point multiplication module, floating-point division module, the floating point number index module.Index module is a comprehensive index of the front three cases into Taylor series for calculating index, the number of iterations can be set to determine the precision
Platform: | Size: 5120 | Author: 周和 | Hits:

[VHDL-FPGA-Verilog] floatadd

Description: 32位浮点数加法，使用的语言是verilog。其中包括的是工程中的v文件。-32-bit floating-point addition, the use of language is verilog. Including is v of the engineering documents.
Platform: | Size: 2048 | Author: 小王 | Hits:

[VHDL-FPGA-Verilog] adder

Description: 能够实现单精度浮点加法运算。输入引脚有：第一运算数，第二运算数，复位信号，时钟信号。输出信号有：运算结果，运算完成标志。(To achieve a single precision floating-point addition operations)
Platform: | Size: 5219328 | Author: 无聊人 | Hits:

[Other] 基于FPGA的单精度浮点数乘法器设计

Description: 《基于FPGA的单精度浮点数乘法器设计》详细介绍了按照IEEE754标准在FPGA上实现单精度浮点加减乘除的方法(The design of single precision floating point multiplier based on FPGA introduces in detail the way of realizing single precision floating point addition, subtraction and multiplication and division based on IEEE754 standard on FPGA.)
Platform: | Size: 2432000 | Author: sisuozheweilai | Hits:

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